Memory system and method for controlling nonvolatile memory with a host memory buffer

ABSTRACT

According to one embodiment, a memory system retrieves write data from a write buffer of a host, and executes a write operation of writing the write data to a write destination location of a write destination block selected from a plurality of blocks. In a case where a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable, the memory system executes a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host. The memory system prohibits releasing a region in the write buffer where the write data is stored until execution of the first read command is completed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 17/572,713, filed Jan. 11, 2022, which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 16/564,376, filed Sep. 9, 2019, which is based upon and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2019-013222, filed Jan. 29, 2019, the entire contents of each of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to technology of controlling a nonvolatile memory.

BACKGROUND

In recent years, memory systems comprising nonvolatile memories have been widely prevalent. As such a memory system, a solid state drive (SSD) based on a NAND flash technology is known.

In the server of a data center, an SSD is used as a storage device.

High I/O performance has been required for the storage device used in a host computing system such as a server.

For this reason, new technologies of enabling the host to directly control a nonvolatile memory in the storage device have been recently proposed.

However, if the burden on the host for controlling the nonvolatile memory in the storage device is increased, sufficient I/O performance may be unable to be thereby obtained. For this reason, implementation of new technologies of reducing the host-side burden is required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a relationship between a host and a memory system according to the embodiments.

FIG. 2 is a diagram illustrating role sharing between the host and the memory system of the embodiments.

FIG. 3 is a block diagram illustrating a configuration example of the memory system of the embodiments.

FIG. 4 is a block diagram illustrating a relationship between a NAND interface and plural NAND flash memory chips, which are provided in the memory system of the embodiments.

FIG. 5 is a block diagram illustrating a configuration example of one block (super block) configured by plural physical block sets.

FIG. 6 is a diagram illustrating the write command applied to the memory system of the embodiments.

FIG. 7 is a diagram illustrating an address record request sent to the host from the memory system of the embodiments.

FIG. 8 is a table illustrating a read command applied to the memory system of the embodiments.

FIG. 9 is a diagram illustrating a quality-of-service (QoS) domain create command applied to the memory system of the embodiments.

FIG. 10 is a diagram illustrating a buffer release request sent to the host from the memory system of the embodiments.

FIG. 11 is a block diagram illustrating a block address and an offset defining a physical address included in each of an address record request and a read command.

FIG. 12 is a block diagram illustrating a relationship between block addresses and offsets in a case where a super block is used.

FIG. 13 is a block diagram illustrating plural QoS domains managed by the memory system of the embodiments.

FIG. 14 is a block diagram illustrating data write processing executed by the host and the memory system of the embodiments.

FIG. 15 is a diagram illustrating a write operation including plural write steps, which is executed by the memory system of the embodiments.

FIG. 16 is a block diagram illustrating data read processing executed by the host and the memory system of the embodiments.

FIG. 17 is a block diagram illustrating the data read processing of reading the data from the write buffer of the host in a case where the write operation of the data designated by the read command is not finished.

FIG. 18 is a block diagram illustrating a relationship between QoS domains and a common flash block pool, which are managed by the memory system of the embodiment.

FIG. 19 is a block diagram illustrating a command number counter managed by the memory system of the embodiments.

FIG. 20 is a flowchart illustrating a procedure of command number counter update processing executed by the memory system of the embodiments.

FIG. 21 is a flowchart illustrating a procedure of a data read operation executed by the memory system of the embodiments.

FIG. 22 is a flowchart illustrating procedures of a data write operation and write buffer release processing executed by the memory system of the embodiments.

FIG. 23 is a flowchart illustrating a procedure of the data read operation executed when the data designated by the read command is readable from both the flash memory and the write buffer of the host.

FIG. 24 is a flowchart illustrating another procedure of the data read operation executed when the data designated by the read command is readable from both the flash memory and the write buffer of the host.

DETAILED DESCRIPTION

Various embodiments will be described hereinafter with reference to the accompanying drawings.

In general, according to one embodiment, a memory system is connectable to a host. The memory system comprises a nonvolatile memory including a plurality of blocks, and a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory.

The controller receives from the host a write command to designate storage location information indicative of a storage location in a write buffer of the host where write data is stored. The controller retrieves the write data from the write buffer of the host, on the basis of the storage location information. The controller executes a write operation of writing the write data to a write destination location of a write destination block selected from the plurality of blocks.

In a case where a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable from the nonvolatile memory, the controller executes a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host. The controller prohibits releasing a region in the write buffer where the write data is stored until execution of the first read command is completed.

First, a relationship between a host and a memory system according to the embodiments will be described with reference to FIG. 1 .

The memory system is a semiconductor storage device configured to write data to a nonvolatile memory and to read data from the nonvolatile memory. The memory system is implemented as a flash storage device 3 based on the NAND flash technology.

The host (host device) 2 is configured to control plural flash storage devices 3. The host 2 is implemented by an information processing apparatus configured to use a flash array composed of plural flash storage devices 3 as a storage. This information processing apparatus may be a personal computer or a server computer.

The flash storage device 3 may be utilized as one of plural flash storage devices provided in the storage array. The storage array may be connected to the information processing device such as a server computer via a cable or a network. The storage array comprises a controller which controls plural storages (for example, plural flash storage devices 3) in the storage array. If the flash storage devices 3 are applied to the storage array, the controller of the storage array may function as the host of the flash storage devices 3.

An example of a case where the information processing apparatus such as a server computer functions as the host 2 will be described below.

The host (server) 2 and plural flash storage devices 3 are interconnected via an interface 50 (internal interconnection). The interface 50 for interconnection is not limited to this, but, PCI Express (PCIe) (registered trademark), NVM Express (NVMe) (registered trademark), Ethernet (registered trademark) or NVMe over Fabrics (NVMeOF) and the like can be used as the interface.

A typical example of the server computer which functions as the host 2 is a server computer (hereinafter called a server) in a data center.

In a case where the host 2 is implemented by the server in the data center, the host (server) 2 may be connected to plural end user terminals (clients) 61 via a network 60. The host 2 can provide various services to the end user terminals 61.

Examples of services which can be provided by the host (server) 2 are (1) Platform as a Service (PaaS) which provides a system running platform to each client (each end user terminal 61), (2) Infrastructure as a Service (IaaS) which provides an infrastructure such as a virtual server to each client (each end user terminal 61), and the like.

A plurality of virtual machines may be executed on a physical server functioning as the host (server) 2. Each of the virtual machines running on the host (server) 2 can function as a virtual server configured to provide various services to a client (end user terminal 61) corresponding to the virtual machine. In each of the virtual machines, an operating system and a user application, which are used by the end user terminal 61 corresponding to the virtual machine, are executed.

A flash translation layer (host FTL) is also executed in the host (server) 2. The host FTL includes a lookup table (LUT), which is an address translation table managing mapping between each of data identifiers (tags) to identify access target data and each of physical addresses of the nonvolatile memory in the flash storage device 3. The host FTL can recognize data placement on the nonvolatile memory in the flash storage device 3 by using the LUT.

Each flash storage device 3 includes a nonvolatile memory such as a NAND flash memory. The nonvolatile memory includes plural blocks each including plural pages. Each of the blocks is a unit of erasing the data, and each of the plural pages is a unit of data write and data read.

The flash storage device 3 can execute low-level abstraction. The low-level abstraction is a function for abstraction of the nonvolatile memory. The low-level abstraction includes a function of assisting the data placement and the like. The example of the function of assisting the data placement may include a function of allocating the write destination block to which the user data from the host 2 is to be written, a function of determining the write destination location (write destination block and location in the write destination block) of the user data, a function of notifying an upper layer (host 2) of the write destination location (block address and offset) to which the user data is written, and the like.

The flash storage device 3 executes various commands received from the host 2. These commands include a write command to write data to the nonvolatile memory in the flash storage device 3 and a read command to read data from the nonvolatile memory. In the embodiments, each of the read commands designates a physical address indicative of the storage location in which the data to be read is stored. This physical address is indicated by a block address of a read target block and an offset (block offset) indicative of a read target storage location in the read target block.

The flash storage device 3 receives from the host 2 read commands each designating the block address of the read target block and the offset indicative of the read target storage location in the read target block, and executes the data read operation in response to each of the received read commands.

FIG. 2 is a diagram for explanation of role sharing between the host and the flash storage device 3.

In the host (server) 2, virtual machines 401 corresponding to plural end users (plural clients) respectively are executed. In each of virtual machines 401, an operating system and a user application 402, which are used by the corresponding client, are executed.

In addition, plural I/O services 403 corresponding to plural user applications 402, respectively, are executed in the host (server) 2. The I/O services 403 may include logical block address (LBA)-based block I/O service, key-value store service, and the like. Each of the I/O services 403 includes a lookup table (LUT) which manages mapping between each of the tags and each of the physical addresses of the flash storage device 3.

The tag is indicative of an identifier which can identify access target data. A typical example of the tag is not limited to this but is a logical address such as LBA. Alternatively, a key of a key-value store, a hash value of this key, or the like may be used as the tag.

The physical address of the flash storage device 3 is an address for identifying a storage location (physical storage location) in the nonvolatile memory incorporated in the flash storage device 3.

In the LBA-based block I/O service, LUT which manages mapping between each of the logical addresses (LBAs) and each of the physical addresses of the flash storage device 3 may be used.

In contrast, in the key-value store service, LUT which manages mapping among each of keys (hash values of the keys), each of the physical addresses of the flash storage devices 3 storing the data corresponding to these keys, and each of data lengths of the data corresponding to the keys, may be used.

Each of the end users can select an addressing method (LBA, the key of the key-value store, the hash value of the key, or the like) to be used.

In the host (server) 2, plural write buffers (WB) 404 corresponding to the plural virtual machines 401, respectively, may be managed. Write data from a certain user application 402 may be temporarily stored in the write buffer (WB) 404 for the virtual machine 401 corresponding to the user application 402.

Transmission of the command from the host (server) 2 to the flash storage device 3 and return of a response of command completion or the like from the flash storage device 3 to the host (server) 2 are executed via an I/O queue 500 which exists in each of the host (server) 2 and the flash storage devices 3.

The flash storage device 3 manages each of plural regions obtained by logically dividing the nonvolatile memory in the flash storage device 3, as QoS domain 601. Each of the QoS domains 601 is a subset of the plural blocks included in the nonvolatile memory. Each of the plural blocks included in the nonvolatile memory belongs to only one QoS domain 601 but the same block does not simultaneously belong to different QoS domains 601.

The QoS domains 601 are identified by identifiers called QoS domain IDs, respectively. The QoS domain IDs are used as plural identifiers for access to the plural regions (plural QoS domains), respectively.

In the embodiments, each write command designates storage location information indicative of a storage location in the write buffer (WB) 404 of the host 2 where data to be written (write data) is stored. In the embodiments, each write command designates the identifier (QoS domain ID) of the region (QoS domain) to which the data is to be written. When the flash storage device 3 receives a write command designating a certain QoS domain ID from the host 2, the flash storage device 3 selects one block of the common block group 602 shared by the plural QoS domains 601 and allocates the selected block as a write destination block for the QoS domain having the QoS domain ID.

The write destination block is indicative of the block to which the data is to be written. The common block group 602 is a common block group including a set of free blocks shared by the plural QoS domains 601.

The free block is indicative of a block in a state (free state) of being capable of being reused (reallocated) as a new write destination block. A typical example of the free block is a block where no valid data is stored. The valid data is indicative of the latest data associated with a tag such as LBA. In other words, the data linked to LUT of the host as the latest data is the valid data. In addition, invalid data is indicative of the data which is not associated with the tag such as LBA. The data which is not linked to LUT of the host 2 is the invalid data. For example, if updated data corresponding to certain LBA is written to the flash storage device 3, previous data corresponding to the LBA becomes invalid data.

The flash storage device 3 retrieves data associated with the received write command from the write buffer (WB) 404 of the host 2 and writes the data to the write destination block allocated for the QoS domain. If a usable write destination block is already allocated for this QoS domain, the above-described operation of allocating one block (free block) of the blocks of the common block group 602 as the write destination block for the QoS domain does not need to be executed. The flash storage device 3 writes the data associated with the received write command to a next usable page in the already allocated write destination block.

When the data associated with the received write command is written to the write destination block, the flash storage device 3 sends to the host 2 a tag of this data and a physical address (block address and offset) indicative of the storage location in the nonvolatile memory to which the data is written as an address record request. The block address is an identifier for identifying the write destination block. Since the nonvolatile memory is generally composed of plural nonvolatile memory chips, a block address of a certain block may be indicated by a chip number of the nonvolatile memory and a block number in the chip. The offset is indicative of a storage location in the write destination block.

The host 2 can update LUT such that the physical address (block address and offset) is associated with the tag of the data, in response to the address record request.

As regards each of the blocks included in each QoS domain, the host 2 can determine whether data stored in each block is valid data or invalid data by using the LUT. In addition, the host 2 can transmit a command (reuse command) to transition a block to which the data is already written to a reusable state (free block) of being reusable as a new write destination block, to the flash storage device 3.

FIG. 3 illustrates a configuration example of the flash storage device 3.

The flash storage device 3 comprises a controller 4 and a nonvolatile memory (NAND flash memory) 5. The flash storage device 3 may also comprise a random access memory, for example, DRAM 6.

The NAND flash memory 5 comprises a memory cell array comprising plural memory cells arranged in a matrix. The NAND flash memory 5 may be a NAND flash memory having a two-dimensional structure or a NAND flash memory having a three-dimensional structure.

The memory cell array of the NAND flash memory 5 includes plural blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 includes plural pages (pages P0 to Pn-1 in this case). The blocks BLK0 to BLKm-1 function as erase units. The blocks may be called erase blocks, physical blocks or physical erase blocks. Pages P0 to Pn-1 are units for a data write operation and a data read operation.

The controller 4 is electrically connected to the NAND flash memory 5 which is a nonvolatile memory via a NAND interface 13 such as Toggle NAND flash interface or Open NAND Flash Interface (ONFI). The controller 4 operates as a memory controller configured to control the NAND flash memory 5. The controller 4 may be realized by a circuit such as a System-on-a-chip (SoC).

As illustrated in FIG. 4 , the NAND flash memory 5 may include plural NAND flash memory chips (NAND flash memory dies). Each of the NAND flash memory chips can operate independently. For this reason, the NAND flash memory chips function as parallel operation units. FIG. 4 illustrates an example of a case where sixteen channels Ch. 1 to Ch. 16 are connected to the NAND interface 13, and two NAND flash memory chips are connected to each of sixteen channels Ch. 1 to Ch. 16. In this case, sixteen NAND flash memory chips #1 to #16 connected to channels Ch. 1 to Ch. 16 may be organized as bank #0, and remaining sixteen NAND flash memory chips #17 to #32 connected to channels Ch. 1 to Ch. 16 may be organized as bank #1. The banks function as parallel operation units for operating plural memory modules in parallel by bank interleaving. In the configuration example of FIG. 4 , a maximum of thirty-two NAND flash memory chips can be urged to execute the parallel operation by sixteen channels and bank interleaving using two banks.

An erase operation may be executed in units of single block (physical block) or units of block group (super block) including a set of plural physical blocks capable of parallel operation. Each block group (one super block) is not limited to this but may include thirty-two physical blocks selected one by one from respective NAND flash memory chips #1 to #32. Each of NAND flash memory chips #1 to #32 may comprise a multiplane structure. For example, when each of NAND flash memory chips #1 to #32 comprises a multiplane structure including two planes, each super block may include sixty-four physical blocks in total selected one by one from sixty-four planes corresponding to NAND flash memory chips #1 to #32.

FIG. 5 illustrates an example of a super block (SB) including thirty-two physical blocks (i.e., physical block BLK2 in NAND flash memory chip #1, physical block BLK3 in NAND flash memory chip #2, physical block BLK7 in NAND flash memory chip #3, physical block BLK4 in NAND flash memory chip #4, physical block BLK6 in NAND flash memory chip #5, . . . , physical block BLK3 in NAND flash memory chip #32).

The write destination block may be either a single physical block or a single super block. Each super block may include only one physical block and, in this case, a single super block is equivalent to a single physical block.

Next, the configuration of the controller 4 of FIG. 3 will be described.

The controller 4 includes a host interface 11, CPU 12, a NAND interface 13, a DRAM interface 14, a direct memory access controller (DMAC) 15, an ECC encode/decode unit 16, and the like. The host interface 11, the CPU 12, the NAND interface 13, the DRAM interface 14, the DMAC 15, and the ECC encode/decode unit 16 are interconnected via the bus 10.

The host interface 11 is a host interface circuit configured to execute communication with the host 2. The host interface 11 may be, for example, a PCIe controller (NVMe controller). Alternatively, when the flash storage device 3 is connected to the host 2 via Ethernet (registered trademark), the host interface 11 may be an NVMe over Fabrics (NVMeOF) controller.

The host interface 11 receives various commands from the host 2. The commands include a write command, a read command, an erase command, a reuse command, a QoS domain create command, and other various commands.

The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, the DRAM interface 14, the DMAC 15, and the ECC encode/decode unit 16. The CPU 12 loads a control program (firmware) from the NAND flash memory 5 or a ROM (not illustrated) to the DRAM 6 in response to power-on of the flash storage device 3 and executes various processing by executing the firmware. The firmware may be loaded into a SRAM in the controller 4, which is not illustrated in the drawings. The CPU 12 can execute command processing for executing various commands from the host 2, and the like. The operations of the CPU 12 can be controlled by the above-described firmware executed by the CPU 12. Several or all parts of the command processing may be executed by dedicated hardware in the controller 4.

The CPU 12 can function as a write control unit 21, a read control unit 22, a copy control unit 23, and a write buffer release control unit 24. Several or all parts of each of the write control unit 21, the read control unit 22, the copy control unit 23, and the write buffer release control unit 24 may also be implemented by dedicated hardware in the controller 4.

The write control unit 21 receives from the host 2 a write command designating the storage location information indicative of the storage location in the write buffer of the host 2 where the write data is stored. The write control unit 21 retrieves the write data from the write buffer of the host 2, based on the storage location information. The write control unit 21 executes the write operation of writing the write data to a write destination location of a write destination block selected from the plural blocks of the NAND flash memory 5.

In the embodiments, the write command of the type designating the physical address indicative of the storage location to which the write data is to be written may be used or the write command of the type which designates the QoS domain ID and the tag but does not designate the physical address may be used.

In a case of using a configuration that the host 2 determines both of the write destination block and the write destination location of this write destination block, the write command of the type designating the physical address indicative of the storage location to which the write data is to be written is used.

In contrast, in a case of using a configuration that the flash storage device 3 determines both of the write destination block and the write destination location of this write destination block, the write command of the type which designates the QoS domain ID and the tag but does not designate the physical address is used.

A case of using a write command of the type which designates the QoS domain ID and the tag but does not designate the physical address will be hereinafter assumed.

The write control unit 21 receives from the host 2 a write command designating the storage location information in the write buffer, the QoS domain ID, and the tag. The tag is an identifier capable of identifying data (user data) to be written and may be, for example, LBA, a key of a key-value store, or a hash value of this key. When the write control unit 21 receives the write command, the write control unit 21 selects one of blocks of the common block group 602, and allocates the selected block as a write destination block for the QoS domain corresponding to the QoS domain ID designated by the write command. The block allocated as the write destination block for the QoS domain may be a physical block or a super block.

In this case, the write control unit 21 may select a block (a physical block or a super block) having the minimum program/erase cycle count. Wear leveling can be thereby executed between the QoS domains. If a usable write destination block is already allocated for this QoS domain, the operation of allocating one of the blocks of the common block group 602 as the write destination block for the QoS domain is not executed.

The write control unit 21 determines a location in the write destination block (i.e., a write destination location) to which the data is to be written, by considering restrictions on page write order, defective pages in the write destination block, and the like. Next, the write control unit 21 retrieves the data (write data) from the write buffer of the host 2, based on the storage location information, and writes the write data to the write destination location of the write destination block. In this case, the write control unit 21 can write not only the write data from the host 2, but also both of the write data and the tag of the write data to the write destination block.

When a whole write destination block of a certain QoS domain is filled with the data, the write control unit 21 allocates one of the blocks of the common block group 602 as a new write destination block for this QoS domain. For example, if an entire portion of a current write destination block is filled with data by write of a part of the write data associated with a certain write command, the write control unit 21 allocates one of the blocks of the common block group 602 as a new write destination block for this QoS domain and writes the remaining part of the write data associated with the write command to the new write destination block.

When the write data is written to the write destination block, the write control unit 21 sends to the host 2 the physical address (block address and offset) indicative of the storage location in the nonvolatile memory to which the data is written as an address record request.

In a case of allocating one physical block as a write destination block, the block address is a block address for identifying the physical block. This block address may be indicated by a chip number and a block number in the chip.

In a case of allocating one super block as a write destination block, the block address is a block address (also called a super block address) for identifying the super block. Different super block addresses may be given to all the super blocks in the flash storage device 3.

The offset is indicative of an offset from the beginning of the write destination block to the write destination location, i.e., an offset of the write destination location with respect to the beginning of the write destination block. The size of the offset from the beginning of the write destination block to the write destination location may be represented by a multiple of the grain having a certain size. Alternatively, the offset may be represented by a page address of a page and a page offset in this page.

The read control unit 22 reads the data designated as the read target data by the read command from the NAND flash memory 5 in accordance with the read command received from the host 2, and transfers the read data to the host 2.

In either of the case using a configuration that the host 2 determines both of the write destination block and the write destination location of this write destination block and the case of using a configuration that the flash storage device 3 determines both of the write destination block and the write destination location of this write destination block, the read command designating the physical address (i.e., block address and offset) can be used.

When the read control unit 22 receives the read command to designate the physical address (i.e., the block address and the offset) from the host 2, the read control unit 22 reads the data from the NAND flash memory 5, based on the block address and the offset. The read target block is specified by the block address. The read target storage location in the block is specified by the offset. The read command may further include QoS domain ID of the read target QoS domain.

In the embodiments, when a read command designating write data (several or all parts of write data) is received from the host 2 before the operation of writing the write data is finished such that the write data becomes readable from the NAND flash memory 5, the read control unit 22 executes a read operation including the operation of reading the write data (several or all parts of write data) from the write buffer of the host 2 and the operation of returning the write data (several or all parts of write data) to the host 2. Thus, in a case where the operation of writing the data designated as the read target data by the read command is not finished and the data cannot be read from the NAND flash memory 5, the read control unit 22 does not return a read error to the host 2 but reads the data from the write buffer of the host 2 and returns the data to the host 2.

In a number of present-day NAND flash memories, a complicated write operation is often executed to reduce program disturb. For this reason, in a number of flash memories of the present-day NAND flash memories, even if the data is written to a certain page in a block, the data written to this page often cannot be read immediately after the write, but the data read from this page can be executed after data write to one or more pages subsequent with this page.

In the NAND flash memory, miniaturization of cells has proceeded, and program disturb that a threshold level of adjacent cells is varied by data write to the cells may occur. For this reason, in the NAND flash memory, a program operation that data write to each cell in a certain page allows the threshold level of each cell in one or more pages immediately before the page to be corrected may be executed in consideration of an influence of the program disturb. If the data is read from the page before the correction is completed, error data different from the original data is read. The timing of completing the correction is different according to the type of the NAND flash memory.

In addition, in the present-day NAND flash memory, the data write operation is often executed by plural write steps including transferring the same write data to the NAND flash memory at plural times. One of examples of the data write operation including plural write steps is a foggy fine write operation.

The data write operation including plural write steps is composed of at least a first-stage write operation such as the foggy write operation and a second-stage write operation such as the fine write operation. The foggy write operation is a write operation of roughly setting a threshold distribution of each memory cell, and the fine write operation is a write operation of adjusting the threshold distribution of each memory cell. Furthermore, an intermediate write operation may be executed between the foggy write operation and the fine write operation.

In addition, in the present-day NAND flash memories, the data write operation is executed in several adjacent word lines back and forth. For example, in a foggy-fine write operation executed in two word lines back and forth, a program sequence of (1) the foggy write operation for a memory cell group connected to the first word line, (2) the foggy write operation for a memory cell group connected to the second word line, (3) the fine write operation for a memory cell group connected to the first word line, (4) the foggy write operation for a memory cell group connected to the third word line, (5) the fine write operation for a memory cell group connected to the second word line, . . . is applied.

Therefore, much time is required from start to end of the write operation of writing certain data.

In the embodiments, if a read command designating write data is received from the host 2 before the operation of writing the write data is finished (for example, both the foggy write operation and the fine write operation are finished) such that the write data becomes readable, the read control unit 22 reads the read target data from the write buffer of the host 2 and returns the read data to the host 2. Therefore, the host 2 can receive desired data from the flash storage device 3 by merely executing simple processing of issuing the read command to the flash storage device 3 without executing the processing of checking whether the data to be read can be read from the NAND flash memory 5 or not and the processing of selectively issuing the read request to the write buffer and the read command to the flash storage device 3.

In response to the copy command received from the host 2, the copy control unit 23 copies data in a certain block allocated for a certain QoS domain to a block (copy destination block) for this QoS domain or the other QoS domain. The copy destination block is a write destination block to which the data already written in the nonvolatile memory is to be written (copied). This copy command may designate a QoS domain ID of the copy source QoS domain, a block address of the copy source block, and a QoS domain ID of the copy destination QoS domain. The copy source block may be a physical block or a super block.

In addition, the host 2 can transmit management data (map data) indicative of whether each data in the copy source block is valid data or invalid data, in units of a predetermined management size (for example, 4 KB), to the flash storage device 3. This map data may be included in the copy command or may be transmitted from the host 2 to the flash storage device 3 apart from the copy command. On the basis of the map data and the copy command received from the host 2, the copy control unit 23 can copy valid data in the copy source block to a block (copy destination block) for this QoS domain or the other QoS domain.

When copying the data (valid data) from the copy source block to the copy destination block is completed, the copy control unit 23 notifies the host 2 of a tag of the data and a copy destination physical address (block address and offset) of the data for each element of the copied data.

In a case where a read command designating the write data which is not readable from the NAND flash memory 5 as the read target data exists, the write buffer release control unit 24 prohibits release of the region in the write buffer where this write data is stored, until execution of this read command is completed. Then, the write buffer release control unit 24 transmits to the host 2 a write buffer release request to release the region in the write buffer where this write data is stored after the execution of this read command is completed.

In other word, when the operation of writing certain write data is finished and thereby the write data becomes readable, the write buffer release control unit 24 determines whether the read operation of reading the write data designated as the read target data by the read command, from the write buffer, and returning the write data to the host 2 is being executed or not. If the read operation is being executed, the write buffer release control unit 24 does not transmit the write buffer release request to the host 2 until the read operation is finished, but transmits the write buffer release request to the host 2 after the read operation has been finished. Therefore, collision (release request/read command collision) between the write buffer release request and the read command that the data determined to be read from the write buffer, the data which is being read from the write buffer, and the like disappear from the write buffer can be avoided.

The NAND interface 13 is a memory control circuit configured to control the NAND flash memory 5 under the control of the CPU 12.

The DRAM interface 14 is a DRAM control circuit configured to control the DRAM 6 under the control of the CPU 12. A memory region in the DRAM 6 is utilized to store the block management table 32. In addition, the memory region of the DRAM 6 can also be used as an internal buffer for temporarily storing the write data and the like. A buffer-less configuration that an internal buffer is not provided in the flash storage device 3 or the capacity of the internal buffer is close to approximately zero may be applied to the flash storage device 3.

The block management table 32 includes plural management tables corresponding to plural blocks in the NAND flash memory 5, respectively. Each of the management tables is used to store management information (metadata) for managing a block corresponding to the management table. The metadata is not limited to this, but may include a rewrite count (number of program/erase cycles), an open/close state, a write destination page range, and the like. The open/close state is indicative of an open state or close state of this block. The open state is indicative of a state where this block is being used as a write destination block. The write destination block implies a write destination block for host write to which the data is written from the host 2 and a write destination block to which the data already written in the nonvolatile memory is copied. The write destination block for data copy is also called a copy destination block.

The close state is indicative of a state where the block is filled with the data and managed as an active block. The write destination page range is indicative of a range of pages on which the write (program) operation is currently executed.

DMAC 15 executes data transfer between the memory (write buffer) in the host 2 and DRAM 6 (internal buffer) under control of the CPU 12. When the write data needs to be transferred from the write buffer of the host 2 to the internal buffer, the CPU 12 designates a transfer source address indicative of a location on the write buffer, data size, and a transfer destination address indicative of a location on the internal buffer to the DMAC 15.

When the data is to be written to the NAND flash memory 5, the ECC encode/decode unit 16 encodes (ECC-encodes) the write data to be written and thereby adds an error-correcting code (ECC) to the data. When the data is read from the NAND flash memory 5, the ECC coding/decoding unit 141 executes error correction of the read data by using ECC added to the read data.

FIG. 6 illustrates a write command applied to the flash storage device 3.

The write command is a command to request the flash storage device 3 to write the data. The write command may include command ID, QoS domain ID, the tag, the length, the write buffer address, and the like.

The command ID is an identifier unique to this command (i.e., this write command). The QoS domain ID is an identifier capable of uniquely identifying the QoS domain to which the data is to be written. A write command transmitted from the host 2 in response to a write request from an application corresponding to a certain end user includes the QoS domain ID designating the QoS domain corresponding to this end user.

The tag is an identifier for identifying write data to be written. The tag may be a logical address such as LBA, a key of a key-value store or a hash value of this key, as described above.

The length is indicative of the length of the write data to be written. The length (data length) may be designated by the number of the above-described granularity (also referred to as Grain), designated by the number of LBA, or designated by bytes.

The write buffer address is storage location information indicative of a storage location in the host memory (write buffer of the host 2) where the write data to be written is stored. The write buffer address is also referred to as a data pointer.

The controller 4 can create the QoS domain having a capacity designated by the QoS domain create command, based on the QoS domain create command received from the host 2. In this case, the controller 4 may secure (reserve) the number of blocks corresponding to the designated capacity, of the common block group 602 illustrated in FIG. 2 , for this QoS domain. A new QoS domain is created every time the host 2 transmits the QoS domain create command.

The controller 4 can manage not only the common block group 602, but also the active block list (active block pool) corresponding to each of the QoS domains.

The state of each block is roughly classified into an active block (block in a closed state) where valid data is stored, and a free block where valid data is not stored and which can be reused as a write destination block. At a certain QoS domain, each of the blocks which are the active blocks is managed by an active block list corresponding to this QoS domain. In contrast, each of the free blocks of each QoS domain is managed by the common block group 602.

When the controller 4 receives a write command to designate a certain QoS domain ID from the host 2, the controller 4 selects one of blocks (free blocks) in the common block group 602 and allocates the selected block to this QoS domain as a write destination block. Furthermore, the controller 4 determines the location (write destination location) in the write destination block. The write destination location in the write destination block is determined in consideration of the restrictions on page write order, the bad pages, and the like. Then, the controller 4 writes the data from the host 2 to the write destination location in the write destination block.

If the whole write destination block is filled with the user data, the controller 4 moves the write destination block to the active block list (active block pool) of this QoS domain. The controller 4 selects again one of blocks (free blocks) in the common block group 602 and allocates the selected block to this QoS domain as a new write destination block.

An upper limit of the number of blocks that can be allocated to a certain QoS domain is limited to the number of blocks corresponding to the capacity of this QoS domain. If one of the blocks of the common block group 602 is allocated to this QoS domain, the controller 4 decrements the current number of blocks that can be allocated to this QoS domain by 1. If this block is returned to the common block group 602 by the reuse command or the erase command designating one of the blocks of this QoS domain, the controller 4 increments the current number of blocks that can be allocated to this QoS domain by 1.

FIG. 7 illustrates an address record request transmitted from the flash storage device 3 to the host 2.

The address record request is used to notify the host 2 of the physical address indicative of the storage location (physical storage location) in the NAND flash memory 5 where the write data associated with the write command is written. The address record request may include QoS domain ID, the tag, the physical address, and the length.

The QoS domain ID is an identifier for identifying the QoS domain to which the write data is written. The tag is the tag included in the write command illustrated in FIG. 6 . The physical address is indicative of a physical storage location where the write data associated with the write command is written. The physical address is indicated by the block address and the offset. The length is indicative of the length of the written write data.

On the basis of the address record request received from the flash storage device 3, the host 2 can update LUT corresponding to this QoS domain such that the physical address (block address and offset) indicative of the storage location where the write data is written is associated with a tag (for example, LBA) of the write data. In addition, the host 2 can manage validity/invalidity management information for each block used in the QoS domain, based on the content of LUT corresponding to each QoS domain. The validity/invalidity management information corresponding to a certain block indicates whether each of the data stored in this block is valid data or invalid data.

FIG. 8 illustrates a read command applied to the flash storage device 3.

The read command is a command to request the flash storage device 3 to read the data. The read command may include the command ID, the QoS domain ID, the physical address, the length, and the read buffer address.

The command ID is an identifier unique to this command (i.e., this read command). The QoS domain ID is an identifier for identifying the QoS domain to which the data to be read is stored. The physical address is indicative of a physical storage location to which the data to be read is stored. The physical address is indicated by the block address and the offset. This block address is a block address of the read target block. The offset is indicative of a read target storage location in the read target block. The length is indicative of the length of the data to be read. The read buffer address is indicative of a location in the host memory (read buffer of the host 2) to which the read data is to be transferred.

FIG. 9 illustrates a QoS domain create command.

The QoS domain create command is a command for creating the QoS domain. The QoS domain create command may include a command ID, a QoS domain ID, and a capacity.

The command ID is an identifier unique to this command (i.e., this QoS domain create command). The QoS domain ID is an identifier of a QoS domain to be created. The capacity is indicative of a capacity which is to be secured for the QoS domain to be created. The controller 4 secures (reserves) the number of blocks corresponding to this capacity from the common block group 602, and allocates one of the secured blocks as the write destination block for this QoS domain in response to the write command designating this QoS domain ID.

FIG. 10 illustrates a write buffer release request sent from the flash storage device 3 to the host 2.

The write buffer release request is used to release a region in the write buffer where data which becomes readable from the NAND flash memory 5 by finishing of the write to the NAND flash memory 5 is stored. The write buffer release request may include the write command ID. The write command ID is an identifier of a write command corresponding to a releasable write data. For example, when writing the write data associated with a certain write command is finished, the controller 4 of the flash storage device 3 may transmit to the host 2 the write buffer release request including the identifier (command ID) of this write command. Alternatively, the write buffer release request may include storage location information indicative of a releasable region in the write buffer.

FIG. 11 illustrates the block address and offset which define the physical address.

The block address designates a certain block BLK. Each of the blocks BLK includes plural pages (page 0 to page n in this case) as illustrated in FIG. 11 .

In a case where the page size (user data storing area of each page) is 16K bytes and the grain is the size of 4 KB, this block BLK is logically divided into 4×(n+1) regions.

Offset +0 is indicative of a first 4 KB area of page 0, offset +1 is indicative of a second 4 KB area of page 0, offset +2 is indicative of a third 4 KB area of page 0, and offset +3 is indicative of a fourth 4 KB area of page 0.

Offset +4 is indicative of a first 4 KB area of page 1, offset +5 is indicative of a second 4 KB area of page 1, offset +6 is indicative of a third 4 KB area of page 1, and offset +7 is indicative of a fourth 4 KB area of page 1.

FIG. 12 illustrates a relationship between the block address and the offset in a case of using a super block.

To simplify the illustration, one superblock SB #1 is assumed to be composed of four blocks BLK #11, BLK #21, BLK #31, and BLK #41. A block address (super block address) of super block SB #1 is SB #1. Four blocks BLK #11, BLK #21, BLK #31, and BLK #41 may be blocks selected from four different NAND flash memories, respectively.

The data are written in order of page 0 of block BLK #11, page 0 of block BLK #21, page 0 of block BLK #31, page 0 of block BLK #41, page 1 of block BLK #11, page 1 of block BLK #21, page 1 of block BLK #31, page 1 of block BLK #41, . . . by the controller 4.

Offset +0 is indicative of a first 4 KB area of page 0 of block BLK #11, offset +1 is indicative of a second 4 KB area of page 0 of block BLK #11, offset +2 is indicative of a third 4 KB area of page 0 of block BLK #11, and offset +3 is indicative of a fourth 4 KB area of page 0 of block BLK #11.

Offset +4 is indicative of a first 4 KB area of page 0 of block BLK #21, offset +5 is indicative of a second 4 KB area of page 0 of block BLK #21, offset +6 is indicative of a third 4 KB area of page 0 of block BLK #21, and offset +7 is indicative of a fourth 4 KB area of page 0 of block BLK #21.

Similarly, offset +12 is indicative of a first 4 KB area of page 0 of block BLK #41, offset +13 is indicative of a second 4 KB area of page 0 of block BLK #41, offset +14 is indicative of a third 4 KB area of page 0 of block BLK #41, and offset +15 is indicative of a fourth 4 KB area of page 0 of block BLK #41.

Offset +16 is indicative of a first 4 KB area of page 1 of block BLK #11, offset +17 is indicative of a second 4 KB area of page 1 of block BLK #11, offset +18 is indicative of a third 4 KB area of page 1 of block BLK #11, and offset +19 is indicative of a fourth 4 KB area of page 1 of block BLK #11.

Offset +20 is indicative of a first 4 KB area of page 1 of block BLK #21, offset +21 is indicative of a second 4 KB area of page 1 of block BLK #21, offset +22 is indicative of a third 4 KB area of page 1 of block BLK #21, and offset +23 is indicative of a fourth 4 KB area of page 1 of block BLK #21.

Similarly, offset +28 is indicative of a first 4 KB area of page 1 of block BLK #41, offset +29 is indicative of a second 4 KB area of page 1 of block BLK #41, offset +30 is indicative of a third 4 KB area of page 1 of block BLK #41, and offset +31 is indicative of a fourth 4 KB area of page 1 of block BLK #41.

For example, if 4K-byte data corresponding to a write command designating certain LBA (LBAx) is written to the location corresponding to offset +8, the controller 4 may return the logical address (=LBAx), the block number (=SB #1), the offset (=+8), and the length (=1) to the host 2 as the response to the write command.

FIG. 13 illustrates plural QoS domains managed by the flash storage device 3.

FIG. 13 explicitly illustrates a case where QoS domain #0, QoS domain #1, QoS domain #2, . . . , QoS domain #n−1 are already created. In FIG. 13 , these QoS domains are represented by squares. A vertical width of a square representing a certain QoS domain is indicative of the capacity of this QoS domain.

User application #0 can make a read/write access to the QoS domain #0 with the read/write command including the QoS domain ID #0 of the QoS domain #0. Similarly, user application #n−1 can make a read/write access to the QoS domain #n−1 with the read/write command including the QoS domain ID #n−1 of the QoS domain #n−1.

FIG. 14 illustrates data write processing executed by the host 2 and the flash storage device 3.

(1) In the host 2, host FTL 701 is executed. The host FTL 701 manages mapping between each of the tags such as LBAs and each of the physical addresses of the flash storage device 3, with LUT. In response to a write request from a certain user application, the host FTL 701 transmits a write command to designate QoS domain ID of a QoS domain corresponding to this user application, to the flash storage device 3. The host FTL 701 needs only to designate the QoS domain ID alone and does not need to designate a block to which the data is to be written or a page to which the data is to be written. For this reason, the host FTL 701 does not need to manage defective blocks, defective pages, and the like in the flash storage device 3.

(2) The controller 4 of the flash storage device 3 selects one of the blocks of the common block group (free block group) 602 shaped by plural QoS domains 601. The controller 4 allocates the selected block as a write destination block for the QoS domain having the QoS domain ID designated by the received write command. In the common block group (free block group) 602, the only free blocks other than the defective blocks may be managed. For example, a block having the least number of program/erase cycles may be selected from the common block group 602. The controller 4 determines the write destination block as the block to which the data is to be written, and further determines a write destination location in the write destination block to which the data is to be written. As described above, if the write destination block for QoS domain is already allocated, the controller 4 needs only to determine the already allocated write destination block as the block to which the data is to be written, and does not need to execute the operation of allocating one of the blocks of the common block group 602 as the write destination block for QoS domain.

(3) The controller 4 transmits to the host 2 a physical address record request including both the block address indicative of the determined write destination block and the offset indicative of the determined write destination location, and thereby notifies the host 2 of the physical address to which the write data associated with this write command is written.

(4) The controller 4 retrieves write data from the write buffer 702 of the host 2, based on the write buffer address included in the write command. The retrieval of the write data from the write buffer 702 may be executed by DMA transfer. Then, the controller 4 executes a data write operation of writing the write data to the write destination location in the write destination block.

(5) After writing the write data is finished such that the write data becomes readable from the NAND flash memory 5, the controller 4 sends to the host 2 a release request to release the region in the write buffer 702 where the write data is stored. This release request may include an identifier of the write command corresponding to the write data having its writing completed. Alternatively, this release request may include a write buffer address indicative of the storage location of the write data and a length of the write data. The host 2 releases the region in the write buffer 702 where the write data is stored, in response to the release request. The released region in the write buffer 702 is usable for storing the other write data, and the like.

FIG. 15 illustrates the data write operation executed by plural write steps including transferring the same write data to the NAND flash memory 5 at plural times.

An example of the foggy fine write operation executed in four word lines back and forth will be described. In addition, it is assumed that the NAND flash memory 5 is a QLC-flash which stores 4-bit data per memory cell. The foggy fine write operation for one specific write destination block (write destination block BLK #1) in the NAND flash memory 5 is executed in the manner described below.

(1) First, write data corresponding to four pages (P0 to P3) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P0 to P3) to plural memory cells connected to the word line WL0 in this write destination block BLK #1 is executed.

(2) Next, write data corresponding to four pages (P4 to P7) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P4 to P7) to plural memory cells connected to the word line WL1 in this write destination block BLK #1 is executed.

(3) Next, write data corresponding to four pages (P8 to P11) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P8 to P11) to plural memory cells connected to the word line WL2 in this write destination block BLK #1 is executed.

(4) Next, write data corresponding to four pages (P12 to P15) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P12 to P15) to plural memory cells connected to the word line WL3 in this write destination block BLK #1 is executed.

(5) When the foggy write operation for the plural memory cells connected to the word line WL3 is finished, the word line of the write target returns to the word line WL0 and the fine write operation for the plural memory cells connected to the word line WL0 can be executed. Then, the write data corresponding to four pages (P0 to P3) that are the same as the write data corresponding to four pages (P0 to P3) used in the foggy write operation for the word line WL0 are transferred again in page unit to the NAND flash memory 5, and the fine write operation for writing the write data corresponding to four pages (P0 to P3) to the plural memory cells connected to the word line WL0 in the write destination block BLK #1 is executed. The foggy fine write operation of pages P0 to P3 is thereby finished. As a result, the data of four pages (P0 to P3) can be read.

(6) Next, write data corresponding to four pages (P16 to P19) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P16 to P19) to plural memory cells connected to the word line WL4 in this write destination block BLK #1 is executed.

(7) When the foggy write operation for the plural memory cells connected to the word line WL4 is finished, the word line of the write target returns to the word line WL1 and the fine write operation for the plural memory cells connected to the word line WL1 can be executed. Then, the write data corresponding to four pages (P4 to P7) that are the same as the write data corresponding to four pages (P4 to P7) used in the foggy write operation for the word line WL1 are transferred again in page unit to the NAND flash memory 5, and the fine write operation for writing the write data corresponding to four pages (P4 to P7) to the plural memory cells connected to the word line WL1 in the write destination block BLK #1 is executed. The foggy fine write operation of pages P4 to P7 is thereby finished. As a result, the data of four pages (P4 to P7) can be read.

(8) Next, write data corresponding to four pages (P20 to P23) are transferred in page unit to the NAND flash memory 5 and the foggy write operation for writing the write data corresponding to four pages (P20 to P23) to plural memory cells connected to the word line WL5 in this write destination block BLK #1 is executed.

(9) When the foggy write operation for the plural memory cells connected to the word line WL5 is finished, the word line of the write target returns to the word line WL2 and the fine write operation for the plural memory cells connected to the word line WL2 can be executed. Then, the write data corresponding to four pages (P8 to P11) that are the same as the write data corresponding to four pages (P8 to P11) used in the foggy write operation for the word line WL2 are transferred again in page unit to the NAND flash memory 5, and the fine write operation for writing the write data corresponding to four pages (P8 to P11) to the plural memory cells connected to the word line WL2 in the write destination block BLK #1 is executed. The foggy fine write operation of pages P8 to P11 is thereby finished. As a result, the data of four pages (P8 to P11) can be read.

FIG. 16 illustrates data read processing executed by the host 2 and the flash storage device 3.

(1) When the host FTL 701 receives the read request from a certain user application, the host FTL 701 retrieves the physical address corresponding to the tag such as LBA designated by the read request by referring to LUT in the host FTL 701. The host FTL 701 transmits to the flash storage device 3 the read command to designate the QoS domain ID of the QoS domain corresponding to this user application, the retrieved physical address (block address and offset), the length, and the read buffer address.

(2) When the controller 4 receives this read command, the controller 4 reads the data from the NAND flash memory 5, based on the block address and offset designated by this read command. Then, the controller 4 transfers the read data to a location in the read buffer 703 of the host 2, which is designated by the read buffer address, by using DMA transfer.

FIG. 17 illustrates the data read processing of reading the data from the write buffer of the host 2 if the write operation of the data designated by the read command is not finished.

(1) When the host FTL 701 receives the read request from a certain user application, the host FTL 701 retrieves the physical address corresponding to the tag such as LBA designated by the read request by referring to LUT in the host FTL 701. The host FTL 701 transmits to the flash storage device 3 the read command to designate the QoS domain ID of the QoS domain corresponding to this user application, the retrieved physical address (block address and offset), the length, and the read buffer address.

(2) When the controller 4 receives this read command, the controller 4 determines whether the write operation of the read target data designated by the read command is finished or not, based on the block address, offset, and length designated by this read command. If the block having the designated block address is a block in a closed state, it is determined that the write operation of the read target data designated by the read command has been finished.

In contrast, if the block having the designated block address is a block in an opened state, it is determined whether the write operation of the read target data has been finished or not, based on a current write destination page range of the block. If the location in this block where the read target data is stored belongs to a page prior to the current write destination page range, it is determined that the operation of writing the read target data is finished. If the location in this block where the read target data is stored belongs to any page in the current write destination page range, it is determined that the operation of writing the read target data is not finished.

In a case where the operation of writing the data designated as the read target data by the read command is not finished and the data cannot be read from the NAND flash memory 5, the controller 4 reads the read target data from the write buffer of the host 2 by using DMA transfer. The location in the write buffer corresponding to each of write data parts written to the block (write destination block) in the opened state may be managed with a write buffer list prepared for each write destination block. In a write buffer address list corresponding to a certain write destination block, the write buffer address where the write data is stored and the offset indicative of the write destination location corresponding to the write data may be recorded for each write data determined to be written to the write destination block. The controller 4 may specify the write buffer address where the read target data is stored, by referring to the write buffer address list corresponding to the write destination block having the block address in the read command.

(3) The controller 4 transfers the data which is read from the write buffer, to a location in the read buffer 703 of the host 2, which is designated by the read buffer address, by using DMA transfer.

FIG. 18 illustrates a relationship between plural QoS domains and the common flash block pool, which is managed by the controller 4 of the flash storage device 3.

In FIG. 18 , two QoS domains alone, i.e., QoS domain #0 and QoS domain #n−1, are illustrated to simplify the illustration. A common flash block pool 801 is a list to manage the above-described common block group 602 shared by the QoS domains.

Flash block pool #0 of the QoS domain #0 is the above-described active block list for management of each of the active blocks belonging to the QoS domain #0.

When the controller 4 receives the write command to designate QoS domain ID #0 of the QoS domain #0, the controller 4 determines whether the write destination block (opened block) for QoS domain #0 is already allocated or not.

If the write destination block (opened block) is not already allocated, the controller 4 allocates a free block in the common flash block pool 801 as the write destination block (opened block) for QoS domain #0. Then, the controller 4 determines the write destination location in the write destination block, and writes the write data associated with the write command to the write destination location in the write destination block.

In contrast, if the write destination block (open block) is already allocated, the controller 4 determines the write destination location in the write destination block, and writes the write data associated with the write command to the write destination location in the write destination block.

When the whole write destination block is filled with the data from the host, the controller 4 manages the write destination block by the flash block pool #0 (i.e., this write destination block is closed), and allocates a free block in the common flash block pool 801 as a new write destination block (opened block) for QoS domain #0.

When the controller 4 receives the copy command designating the copy source QoS domain indicative of the QoS domain ID #0, the block address of the copy source block, and the copy destination QoS domain indicative of the QoS domain ID #0, the controller 4 determines whether the copy destination block (opened block) for QoS domain #0 is already allocated or not.

If the copy destination block (opened block) for QoS domain #0 is not already allocated, the controller 4 allocates a free block in the common flash block pool 801 as the copy destination block (opened block) for QoS domain #0. Then, the controller 4 selects the block in the flash block pool #0 as the copy source block, based on the block address of the copy source block, and copies the data in the selected copy source block to the copy destination block. If the map data is received from the host 2, the controller 4 copies each of valid data in the selected copy source block to the copy destination block, based on the map data.

In contrast, if the copy destination block is already allocated, the controller 4 copies the data in the selected copy source block to the copy destination block.

If the whole copy destination block is filled with the data from the host, the controller 4 manages the copy destination block by the flash block pool #0 (i.e., the copy destination block is closed) and allocates a free block in the common flash block pool 801 as a new copy destination block (opened block) for QoS domain #0.

If the whole data in one of the blocks belonging to the QoS domain #0 become invalid data by the write operation of updated data or the data copy operation, the host 2 transmits a reuse command to designate the block address of this block to the flash storage device 3.

When the controller 4 receives the reuse command from the host 2, the controller 4 returns this block in the flash block pool #0 designated by the reuse command to the common flash block pool 801 and thereby sets this block to be in a reusable state of being usable as a new write destination block (or copy destination block) for any QoS domain.

When the whole data in one of the blocks belonging to the QoS domain #0 become invalid data by the write operation of updated data or the data copy operation, the host 2 may transmit an erase command to designate the block address of this block to the flash storage device 3. When the controller 4 receives the erase command from the host 2, the controller 4 executes the erase operation for this block in the flash block pool #0 designated by the erase command, returns this block to the common flash block pool 801, and thereby sets this block to be in a reusable state of being usable as a new write destination block (or copy destination block) for any QoS domain.

In QoS domain #n−1, too, the controller 4 executes allocation of the write destination block/copy destination block, processing of managing the write destination block/copy destination block filled with the data by the flash block pool #n−1, processing of returning the block designated by the reuse command/erase command to the common flash block pool 801, and the like.

FIG. 19 illustrates the block management table 32 including a command number counter, which is managed by the controller 4.

For example, in the block management table 32 corresponding to the block BLK #1, a command number counter (hereinafter called an in-flight command number counter) is added as metadata for managing the state of the block BLK #1.

The in-flight command number counter may be prepared for each write command. In this case, the in-flight command number counter value corresponding to a certain write command ID is used to determine whether the region in the write buffer where the write data associated with this write command is stored can be released or not. The controller 4 manages the in-flight command number counter for each of the write destination blocks.

It is assumed that a certain write command is received and the write data associated with this write command is written to write destination block BLK #1. In this case, in the block management table 32 corresponding to the write destination block BLK #1, an in-flight command number counter corresponding to the write command ID of this write command is managed.

The controller 4 executes initial settings of setting the in-flight command number counter value at a value obtained by adding 1 to the number of times of the write step necessary for the data write operation. In a case of writing the write data associated with this write command to the write destination block BLK #1 by the foggy-fine write operation including two write steps, the number of times of write steps necessary for the data write operation is two. The reason for adding 1 to the number of times of the write steps is that a retry of the write operation is required due to a write error.

Every time one write step is finished, the controller 4 decrements the in-flight command number counter value by 1.

If the data write operation is finished such that the write data becomes readable, the controller 4 decrements the in-flight command number counter value by 1.

In a case where the read command designating the write data (several or all parts of the write data) as the read target data is received from the host 2 during the execution of the write operation of the write data, the controller 4 increments the in-flight command number counter value by 1.

When the operation of reading the read target data designated by the read command from the write buffer and returning the data to the host 2 is finished, the controller 4 decrements the in-flight command number counter value by 1.

If the retry of the write operation is required due to a write error, the controller 4 increments the in-flight command number counter value by the number of times of write steps necessary for the retry of the write operation.

When the in-flight command number counter value becomes zero, the controller 4 transmits to the host 2 the write buffer release request to release the region in the write buffer where this write data is stored. The write buffer release request includes the command ID of this write command.

The in-flight command number counter may be prepared for each minimum write unit such as 4 KB instead of each write command. If the in-flight command number counter is prepared per minimum write unit such as 4 KB, the controller 4 may transmit the write buffer release request to release the region in the write buffer where the write data is stored to the host 2 when all of the plural in-flight command number counter values corresponding to whole write data corresponding to a certain write command become zero.

Thus, the controller 4 may transmit the write buffer release request in the minimum write unit such as 4 KB to the host 2 instead of transmitting the write buffer release request in the write command unit to the host 2.

The flowchart of FIG. 20 illustrates a procedure of in-flight command number counter update processing executed by the controller 4.

The controller 4 first sets the in-flight command number counter value to the number of times of the write steps necessary for the data write operation (i.e., number of times of data transfer) (step S11). Then, the controller 4 increments the in-flight command number counter value by 1 for retry of the write operation for error (step S12). The controller 4 starts a write operation of writing the write data associated with the received write command to the write destination block (step S13).

Every time one write step for the write data is finished (YES in step S14), the controller 4 decrements the in-flight command number counter value by 1 (step S15). The controller 4 determines whether the data write operation is finished such that the write data becomes readable from this write destination block, or not (step S16).

When the data write operation is finished such that the write data becomes readable from this write destination block (YES in step S16), the controller 4 decrements the in-flight command number counter value by 1 (step S17).

When the read command designating the write data as the read target data is received during the execution of the data write operation (YES in step S18), the controller 4 increments the in-flight command number counter value by 1 (step S19). When the execution of the read command is completed (YES in step S20), the controller 4 decrements the in-flight command number counter value by 1 (step S20 a).

If a write error occurs (YES in step S20 b), the controller 4 increments the in-flight command number counter value by the number of times of write steps necessary for the retry of the write operation (i.e., number of times of data transfer necessary for the retry) (step S20 c).

The flowchart of FIG. 21 illustrates a procedure of the data read operation.

When the controller 4 receives the read command from the host 2 (YES in step S21), the controller 4 determines whether the data designated as the read target data by the read command can be read from the NAND flash memory 5 or not (step S22).

In step S22, the controller 4 determines whether the block having the block address designated by the read command is in a closed state or an opened state. In a case where the block is in a closed state, the write operation of the data designated as the read target data has been already finished. The controller 4 therefore determines that the read target data is readable from the NAND flash memory 5.

In contrast, if this block is in an opened state, the controller 4 determines whether or not the location in this block where the read target data is stored belongs to a page prior to the current write destination page range of this block. If the location in this block where the read target data is stored belongs to a page prior to the current write destination page range of this block, the write operation of the data designated as the read target data has been already finished. The controller 4 therefore determines that the read target data is readable from the NAND flash memory 5.

If the location in this block where the read target data is stored does not belong to a page prior to the current write destination page range of this block but belongs to any page in the current write destination page range, the write operation of the data designated as the read target data is not finished. The controller 4 therefore determines that the read target data is not readable from the NAND flash memory 5.

If the read target data can be read from the NAND flash memory 5 (YES in step S21), the controller 4 reads the read target data from the NAND flash memory 5 and returns the read data to the host 2 (step S23).

If the read target data cannot be read from the NAND flash memory 5 (NO in step S21), i.e., if the read command designating the write data (several or all parts of the write data) as the read target data is received before the operation of writing the write data is finished such that the write data becomes readable, the controller 4 prohibits the release of the region in the write buffer where the write data is stored (step S24). In this case, even if the operation of writing the write data is finished such that the write data becomes readable, the controller 4 does not transmit to the host 2 a write buffer release request to release the region in the write buffer where the write data is stored. In step S24, the controller 4 may prohibit the release of the region in the write buffer where the write data is stored, by incrementing the in-flight command number counter value corresponding to the write command of the write data by 1.

The controller 4 reads the read target data from the write buffer of the host 2 and returns the read target data to the host 2 (step 325). When the data read operation of step S25 is finished, i.e., when the execution of the read command is completed, the controller 4 cancels the release prohibit state of the region in the write buffer where the write data is stored (step S26). In step S26, the controller 4 may cancel the release prohibit state of the region in the write buffer where the write data is stored, by decrementing the in-flight command number counter value corresponding to the write command of the write data by 1.

FIG. 22 is a flowchart illustrating procedures of a data write operation and write buffer release processing.

When the controller 4 receives from the host 2 the write command designating the storage location information indicative of the storage location in the write buffer where the write data is stored (step S31), the controller 4 retrieves the write data from the write buffer, on the basis of the storage location information (step S32). The controller 4 executes the write operation of writing the write data to a write destination location in a write destination block selected from the plural blocks of the NAND flash memory 5 (step S33).

When the write operation is finished such that the write data becomes readable (YES in step S34), the controller 4 determines whether the read command designating the write data (several or all parts of the write data) as the read target data is already received and the read operation including both of an operation of reading the read target data from the write buffer and an operation of returning the read target data to the host 2 is being executed or not (step S35).

If the read operation is being executed (YES in step S35), the controller 4 prohibits the release of the region in the write buffer where the write data is stored. That is, the controller 4 does not transmit to the host 2 the write buffer release request to release the region in the write buffer where the write data is stored, but delays issuing the write buffer release request until the read command is completed, i.e., the read operation is finished (steps S36 and S37).

When this read operation is finished (YES in step S37), i.e., when the execution of this read command is completed, the controller 4 transmits to the host 2 the write buffer release request to release the region in the write buffer where the write data is stored (step S38).

The flowchart of FIG. 23 illustrates a procedure of the data read operation executed when the data designated by the read command is readable from both the flash memory and the write buffer of the host.

When the controller 4 receives the read command from the host 2 (YES in step S41), the controller 4 determines whether the read target data designated by the read command can be read from the write destination block and the read target data exists in the write buffer or not (step S42).

For example, in a case where the read command designating the write data (several or all parts of the write data) as the read target data is received during a period from the finish of the write operation of writing the write data to the write destination block to the transmission of the write buffer release request corresponding to the write data, the controller 4 may determine that the read target data can be read from the write destination block and that the read target data exists in the write buffer.

In a case where the read target data designated by the read command can be read from the write destination block and the read target data exists in the write buffer (YES in step S42), the controller 4 executes the read operation including both of an operation of reading the read target data from the write buffer and an operation of returning the read target data to the host 2 (step S43).

In general, data transfer between the host 2 and the flash storage device 3 can be executed at a high speed. Therefore, read latency can be reduced by reading the read target data from the write buffer.

The controller 3 prohibits the release of the region in the write buffer where the write data is stored until the execution of the read command is completed, i.e., until the read operation is finished (step S44). That is, the controller 4 does not transmit to the host 2 the write buffer release request to release the region in the write buffer where the write data is stored while the read operation is executed. The read target data can be therefore held in the write buffer until the operation of reading the read target data which are several parts or all parts of the write data is finished.

The flowchart of FIG. 24 illustrates another procedure of the data read operation executed when the data designated by the read command is readable from both the flash memory and the write buffer of the host.

The data read operation described with reference to the flowchart of FIG. 23 reads the read target data from the write buffer to give priority to the reduction in read latency. To give priority to the release of the region in the write buffer where readable data is stored as soon as possible, in the data read operation described with reference to the flowchart of FIG. 24 , the read target data is read, not from the write buffer, but from the write destination block as described below.

When the controller 4 receives the read command from the host 2 (YES in step S51), the controller 4 determines whether the read target data designated by the read command can be read from the write destination block and the read target data exists in the write buffer or not (step S52).

For example, if the read command designating the write data (several or all parts of the write data) as the read target data is received during a period from the finish of the write operation of writing the write data to the write destination block to the transmission of the write buffer release request corresponding to the write data, the controller 4 may determine that the read target data can be read from the write destination block and that the read target data exists in the write buffer.

In a case where the read target data designated by the read command can be read from the write destination block and the read target data exists in the write buffer (YES in step S52), the controller 4 executes the read operation including both of an operation of reading the read target data from the write destination block and an operation of returning the read target data to the host 2 (step S53). In this case, since the controller 4 does not need to maintain the write data designated as the read target data, in the write buffer, the controller 4 can transmit to the host 2 a release request to release the region in the write buffer where the write data is stored before the start of the read operation or during the execution of the read operation.

In the flash storage device 3 of the embodiments, not only the above-described write command, but write commands of the following types can also be used.

<Write Command to Designate Block Address>

The write command may include the command ID, the QoS domain ID, the physical address, the tag, the length, the write buffer address, and the like.

The command ID is an identifier unique to this command (i.e., this write command). The QoS domain ID is an identifier capable of uniquely identifying the QoS domain to which the data is to be written. A write command transmitted from the host 2 in response to a write request from an application corresponding to a certain end user includes the QoS domain ID designating the QoS domain corresponding to this end user.

The physical address designates a block address of the block to which the data is to be written, and does not designate a location in the block (for example, page address and page offset).

The tag is an identifier for identifying write data to be written. The tag may be a logical address such as LBA, a key of a key-value store or a hash value of this key, as described above.

The length is indicative of the length of the write data to be written. The length (data length) may be designated by the number of grain (Grain), the number of LBA, or the byte.

The write buffer address is indicative of a location in the host memory (write buffer of the host 2) where the write data to be written is stored. The write buffer address is also referred to as a data pointer.

When the controller 4 receives the write command from the host 2, the controller 4 determines the write destination location in the block having the block address designated by the write command. The write destination location is determined in consideration of the restrictions on page write order, the bad pages, and the like. Then, the controller 4 writes the data from the host 2 to the determined write destination location in the block having the block address designated by the write command.

In a case of using the write command of this type, the host 2 may require the flash storage device 3 to allocate the block for specific QoS domain by sending the block allocate command to the flash storage device 3. The block allocate command designates the QoS domain ID. When the controller 4 receives a block allocate command, the controller 4 selects one of blocks (free blocks) in the common block group 602 and allocates the selected block to this QoS domain as a write destination block. The controller 4 notifies the host 2 of the block address of the allocated block. The host 2 can transmit the write command designating the block address of the allocated block to the flash storage device 3.

<Write Command to Designate Block Address and Offset>

The write command may include the command ID, the QoS domain ID, the physical address, the tag, the length, the write buffer address, and the like.

The command ID is an identifier unique to this command (i.e., this write command). The QoS domain ID is an identifier capable of uniquely identifying the QoS domain to which the data is to be written. A write command transmitted from the host 2 in response to a write request from an application corresponding to a certain end user includes the QoS domain ID designating the QoS domain corresponding to this end user.

The physical address designates a block address of the block to which the data is to be written, and offset indicative of a write destination location in the block (for example, page address and page offset).

The tag is an identifier for identifying write data to be written. The tag may be a logical address such as LBA, a key of a key-value store or a hash value of this key, as described above.

The length is indicative of the length of the write data to be written. The length (data length) may be designated by the number of grain (Grain), the number of LBA, or the byte.

The write buffer address is indicative of a location in the host memory (write buffer of the host 2) where the write data to be written is stored.

As described above, according to the embodiments, in a case where the operation of writing the data designated as the read target data by the read command is not finished and the data cannot be read from the NAND flash memory 5, the data is read from the write buffer of the host 2 and returned to the host 2. Therefore, the host 2 can receive desired data from the flash storage device 3 by merely executing simple processing of issuing the read command to the flash storage device 3 without executing the processing of checking whether the data to be read can be read from the NAND flash memory 5 or not and the processing of selectively issuing the read request to the write buffer and the read command to the flash storage device 3.

Furthermore, release of the region in the write buffer where this write data is stored is prohibited until the execution of the read command is completed. Therefore, collision (release request/read command collision) between the write buffer release request and the read command that the data determined to be read from the write buffer, the data which is being read from the write buffer, and the like disappear from the write buffer can be avoided. Then, a release request to release the region in the write buffer where the write data is stored is transmitted to the host after the execution of the read command is completed. The burden on the host 2 side for release control of the write buffer can also be therefore reduced.

In the embodiments, in a case where the read command designating the write data as the read target data is received from the host 2 before the operation of writing the write data is finished such that the write data becomes readable from the NAND flash memory 5, the controller 4 reads the read target data from the write buffer of the host 2. In another embodiment, however, if the read command designating the write data as the read target data is received from the host 2 before the operation of writing the write data is finished such that the write data becomes readable from the NAND flash memory 5, the controller 4 may transmit to the host 2 the transfer request to require the read target data to be returned from the write buffer as a response to the read command. This transfer request may include storage location information indicative of the location in the write buffer where the read target data are stored.

In response to reception of the transfer request, the host FTL 701 of the host 2 reads the read target data from the write buffer and transfers the read target data to the read buffer. Then, the host FTL 701 returns a response to the transfer request to the flash storage device 3. The controller 4 may handle reception of this response as completion of execution of this read command. In this case, the controller 4 prohibits the release of the region in the write buffer where the write data is stored until this response is received. After receiving this response, the controller 4 transmits to the host 2 a release request to release the region in the write buffer where the write data is stored. In this case, the controller 4 may transmit a release request to release the region in the write buffer where the write data is stored to the host 2 after the operation of writing the write data is completed such that the write data becomes readable from the NAND flash memory 5 and after this response is received.

In the embodiments, the NAND flash memory has been illustrated as a nonvolatile memory. However, the functions of the present embodiment are also applicable to various other nonvolatile memories such as a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM) and a ferroelectric random access memory (FeRAM).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

What is claimed is:
 1. A memory system connectable to a host, the memory system comprising: a nonvolatile memory including a plurality of blocks; and a controller configured to control the nonvolatile memory, wherein the controller is configured to: receive from the host a write command to designate storage location information indicative of a storage location in a write buffer of the host where write data is stored, the write buffer of the host existing in the host; retrieve the write data from the write buffer of the host, based on the storage location information; execute a write operation of writing the write data to a write destination location of a write destination block selected from the plurality of blocks; and in a case that a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable from the nonvolatile memory, transmit to the host a transfer request, the transfer request requiring the read target data to be returned from the write buffer as a response to the first read command.
 2. The memory system of claim 1, wherein the transfer request designates storage location information indicative of a storage location in the write buffer of the host where the read target data is stored.
 3. The memory system of claim 1, wherein the host is configured to transmit a response to the transfer request to the memory system, and the controller is configured to delay transmitting a release request to the host until the response to the transfer request is received from the host, the release request being a request releasing a region in the write buffer where the write data is stored.
 4. The memory system of claim 3, wherein the controller is configured to transmit the release request to the host when the response to the transfer request is received from the host.
 5. The memory system of claim 1, wherein the host is configured to transmit a response to the transfer request to the memory system, and the controller is configured to, in a case that the response to the transfer request is received from the host and the write operation is finished such that the write data becomes readable from the nonvolatile memory, transmit a release request to the host, the release request being a request releasing a region in the write buffer where the write data is stored.
 6. The memory system of claim 1, wherein the controller is configured to, in a case that read target data designated by a read command received from the host is readable from the write destination block and the read target data exists in the write buffer of the host, execute a read operation including an operation of reading the read target data from the write destination block and an operation of returning the read target data to the host.
 7. The memory system of claim 1, wherein the write operation of the write data is executed by plural write steps including transferring the write data to the nonvolatile memory at plural times, and the controller is configured to: set a first counter value to a value obtained by adding 1 to a number of times of the write steps necessary to the write operation; decrement the first counter value by 1 every time one write step is finished; decrement the first counter value by 1 when the write operation is finished such that the write data becomes readable; increment the first counter value by 1 when receiving the first read command during execution of the write operation; decrement the first counter value by 1 when the read operation is finished; and transmit to the host a release request to release a region in the write buffer where the write data is stored when the first counter value becomes zero.
 8. A method of controlling memory system including a nonvolatile memory, the nonvolatile memory including a plurality of blocks, the method comprising: receiving from a host a write command to designate storage location information indicative of a storage location in a write buffer of the host where write data is stored, the write buffer of the host existing in the host; retrieving the write data from the write buffer of the host, based on the storage location information; executing a write operation of writing the write data to a write destination location of a write destination block selected from the plurality of blocks; and in a case that a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable from the nonvolatile memory, transmitting to the host a transfer request, the transfer request requiring the read target data to be returned from the write buffer as a response to the first read command.
 9. The method of claim 8, wherein the transfer request designates storage location information indicative of a storage location in the write buffer of the host where the read target data is stored.
 10. The method of claim 8, wherein the host is configured to transmit a response to the transfer request to the memory system, and the method further comprises: delaying transmitting a release request to the host until the response to the transfer request is received from the host, the release request being a request releasing a region in the write buffer where the write data is stored.
 11. The method of claim 10, further comprising: transmitting the release request to the host when the response to the transfer request is received from the host.
 12. The method of claim 8, wherein the host is configured to transmit a response to the transfer request to the memory system, and the method further comprises: in a case that the response to the transfer request is received from the host and the write operation is finished such that the write data becomes readable from the nonvolatile memory, transmitting a release request to the host, the release request being a request releasing a region in the write buffer where the write data is stored.
 13. The method of claim 8, wherein the write operation of the write data is executed by plural write steps including transferring the write data to the nonvolatile memory at plural times, and the method further comprises: setting a first counter value to a value obtained by adding 1 to a number of times of the write steps necessary to the write operation; decrementing the first counter value by 1 every time one write step is finished; decrementing the first counter value by 1 when the write operation is finished such that the write data becomes readable; incrementing the first counter value by 1 when receiving the first read command during execution of the write operation; decrementing the first counter value by 1 when the read operation is finished; and transmitting to the host a release request to release a region in the write buffer where the write data is stored when the first counter value becomes zero. 